Reduction of instantaneous power by ripple scan clocking
One significant obstacle in scan testing is that the associated power consumption during test can far exceed that of normal functional operation. Consequently, high power levels may result in circuit failure and affect testability. Although most research in the past has focused mainly on reducing average power or total energy consumed during test, instantaneous power is also increasing and posing a serious threat for the ability of the chip to be tested in a manufacturing test floor—or worst in field testing using Built-In-Self-Test (BIST) where battery-powered applications lack the supply voltage robustness of automated test equipment (ATE). This research focuses on the design of a flip-flop that is the cornerstone of a novel scan clocking architecture inspired by the need to reduce instantaneous power during scan. The research presented here also explores the challenges of performing scan at ultra-low voltage levels and discusses the advantages of using the Ripple Scan clocking architecture for implementing scan at the lowest possible voltage. In doing so, energy per scan operation is reduced as well. This reduction in energy is achieved without compromising the scan frequency based on new clocking enhancements to the proposed Ripple Scan architecture. (Abstract shortened by UMI.) ^
Joshi, Kirti, "Reduction of instantaneous power by ripple scan clocking" (2005). ETD Collection for University of Texas, El Paso. AAI1427691.