Implementation of a processing element for the reconfigurable data path processor (RDPP)
Abstract
The University of Texas at El Paso has collaborated with the University of New Mexico Microelectronics Research Center and NASA's Goddard Space Flight Center in developing hardware for the Reconfigurable Data Path Processor (RDPP). The RDPP is a Very Large Scale Integration (VLSI) processor chip imagined as an ultra-low power, radiation-tolerant device for data-intensive, streaming applications aboard spacecraft. Reconfigurable data path processing is an important issue in VLSI design because it allows a chip to perform different operations via fall through approaches. Only the input bits need reconfiguring, which allows the RDPP to operate as soft-hardware. Cadence's Signal Processing Worksystem (SPW) is a software program that provides tools, which allow capture, simulation, test, and implementation of a wide range of digital signal processing, communication, and VLSI designs. In this thesis, SPW has been used to implement and simulate the RDPP processing element (PE), verifying and validating the operation of the RDPP's PE.
Subject Area
Electrical engineering
Recommended Citation
Nevarez, Micaela, "Implementation of a processing element for the reconfigurable data path processor (RDPP)" (2005). ETD Collection for University of Texas, El Paso. AAI1428064.
https://scholarworks.utep.edu/dissertations/AAI1428064