A high speed dynamic CMOS flash analog to digital converter
A high speed dynamic analog to digital converter (ADC) was presented in 0.24μmm process using BSIM3 model parameters. High performance comparators are used at very high frequencies containing lot of transistors. Traditionally ROM encoder is used as encoder for high speed applications. ROM encoder inserts lot of signal delay and at GHz range ROM encoder suffers with nonlinearities. This research proposed two designs, static fat tree ADC and dynamic fat tree ADC. The important component in ADC is comparator. Comparator was designed using simple CMOS inverter, thus by reducing transistor count, power and die area. ADC with static fat tree encoder consumes less power and gives less propagation delay where as the ADC with dynamic fat tree gave good high speed performance with very low propagation delay. Because of its high speed performance it consumes more power. The dynamic fat tree ADC used a dynamic logic concept called domino logic in encoder. Domino logic needs N+2 transistors for N-input logic, the dynamic logic used in dynamic fat tree ADC uses N+1 transistors. ^ Proposed designs shown differential nonlinearity and integral nonlinearity less than 0.5LSB up to 500MHz clock frequency. The dynamic fat tree circuit shows good performance in terms of high speed with propagation delay of 144psec, where as the conventional ROM encoder had shown propagation delay of 4.6nsec. The static fat tree circuit had shown good performance in terms of power consumption, 2.21mW. The dynamic fat tree converter consumes 5.62mW due to its high speed. ^
Engineering, Electronics and Electrical
Allu, Ramakrishna Rao, "A high speed dynamic CMOS flash analog to digital converter" (2006). ETD Collection for University of Texas, El Paso. AAI1435318.