Quaternary logic gates

Sai Kanchibhotla, University of Texas at El Paso

Abstract

Advantages, such as improved interconnection routing, result from the use of multi-valued logic (MVL) in modern chip design. However, to make best use of these approaches, mixed radix systems using both multi-valued and binary logic are more appropriate than the use of only multi-valued logic. Therefore, in the development of a MVL library it is necessary to provide encoding and decoding circuitry to perform the required conversion between multi-valued and binary logic signals on for instance a bus and pre- and post-processing binary logic circuits as well as basic MVL and binary gates. ^ In this thesis the basic quaternary logic required to develop an MVL library, is developed and tested. The library includes simple encoder and decoder circuits using MOSFET's as well as, an AND, an OR and an INVERTER quaternary logic gates. The conversion circuits from multi-valued to binary logic and binary to multi-valued logic can be designed in both voltage mode and current mode. The circuits designed here are of the voltage mode type. ^ In addition to the above, circuits are developed to implement the Boolean equation &parl0;A+B*C&parr0; using quaternary logic gate structures. The quaternary output generated from the Boolean function is then converted to binary using the decoder circuitry. Simulation results along with circuit schematic and waveforms are presented, and the accuracy of the waveforms is verified, the accuracy of the waveforms is verified. ^

Subject Area

Engineering, Electronics and Electrical

Recommended Citation

Kanchibhotla, Sai, "Quaternary logic gates" (2003). ETD Collection for University of Texas, El Paso. AAIEP10361.
http://digitalcommons.utep.edu/dissertations/AAIEP10361

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