Design of a fast convolution masking chip using Altera technology
When extended to two-dimensional images, convolution is often expressed in the form referred to as convolutional masking. This latter technique can be used to filter out or amplify certain features in a digital image. ^ Convolution masking is a slow shift and add procedure which reduces the efficiency of the chip and decreases the speed of chip operation. ^ This thesis presents a design for an Altera chip to perform fast convolution masking. Enhanced speed is achieved by transferring the multiplication operation to the chip setup process, since this is a point where the operating speed is less critical. This transferred process relies on the observation that a particular set of convolutional multiplicands, known as mask weights, are used in many operations before being changed. This feature suggested that multiplication lookup tables could be generated during the setup time using the mask weights and stored in a Random Access Memory (RAM). Thus the multiplication operation can be reduced to a reference into a lookup table using the other multiplicand (the image value). Further reduction was realized by using the Distributive Law of Multiplication to partition the multiplication process into two parallel operations, one on a lower pixel nibble and one on a higher pixel nibble. The speed of the operation is limited only by inherent delays in the components used. ^
Engineering, Electronics and Electrical
Revathi, Bindingnavaley Padma, "Design of a fast convolution masking chip using Altera technology" (2003). ETD Collection for University of Texas, El Paso. AAIEP10374.