Development of binary equivalent quaternary gates

Geetha Sandasani, University of Texas at El Paso

Abstract

Most digital circuits use two levels to carry information. Multiple-valued logic implementations, however, may be advantageous. Multiple-valued logic can provide improved circuit interconnections, reduced chip area, and increased bus efficiency since more logic levels are used per line, as compared to conventional binary logic. However, disadvantages also exist. For instance, discrepancies can exist between the outputs of binary and quaternary logic circuits. ^ In this thesis, a binary-equivalent quaternary AND/OR circuit is developed and verified. A circuit to produce basic quaternary outputs serves as the front end of this circuit. Discrepancies between binary and quaternary logic are then addressed to generate the desired binary-equivalent quaternary logic outputs. Circuit schematics explaining the operation of each block of the circuit are presented along with tables that compare the outputs of binary and quaternary logic. Simulation results and waveforms have also been presented and verified. ^

Subject Area

Engineering, Electronics and Electrical

Recommended Citation

Sandasani, Geetha, "Development of binary equivalent quaternary gates" (2004). ETD Collection for University of Texas, El Paso. AAIEP10602.
http://digitalcommons.utep.edu/dissertations/AAIEP10602

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