Low power design techniques for data acquisition
Semiconductor technology advancement continues to lead to smaller device geometries. Digital circuits have benefited from the technology scaling whereas analog circuits often suffer in terms of performance and noise immunity. As functionality continues to be integrated onto systems-on-chips, analog circuits consume increasingly more power than digital circuits and the objective of this dissertation is to explore low power techniques in the context of both digital and analog circuits residing on the same silicon real estate. As natural signals are in analog form, a necessity exists to convert these into digital form and then back again in order to exploit the advances of digital processing. As a part of this dissertation, a Digital-to-Analog Converter (DAC) is explored in the context of requirements of both low power consumption and high voltage and temporal resolution. On on-going collaboration with SPAWAR, Navy San Diego has provided guidance for challenging electronics applications - including magnetometers and biomedical sensors. The proposed design implements subthreshold rad-hard level shifters and low power DACs for a NAVY patented sensor - serving as a showcase application. The DAC was designed for TSMC 0.25&mgr;m CMOS technology as captured in Virtuoso Cadence - providing a suite of silicon development and evaluation tools required to evaluate the circuits and chips designed and fabricated in the course of this research. The final implementation of the chip is demonstrated through layout and extracted simulation to provide high performance, while maintaining a reasonable footprint and operating with low power when compared to other reported commercial and research DACs.
Computer Engineering|Electrical engineering
Palakurthi, Praveen Kumar, "Low power design techniques for data acquisition" (2015). ETD Collection for University of Texas, El Paso. AAI3682479.