Date of Award
Master of Science
Synchronization has always been an essential feature in electronic circuits, in which functionality is achieved by an appropriate flow of data with respect to time. An ideal concept of logic design would require every operation to happen instantly; however, the application of this principle to electronics is governed by the laws of physics, which influence the time to execute a process. In fact, the speed at which a microprocessor can perform logic operations is determined by the time that charging and discharging capacitive loads requires, and the time that electric signals spend when traveling through the circuitry. Consequently, the variation of capacitance over the circuit, and the disparity of wiring result in a disaccord at the time new data are ready. As a solution for these irregularities, a clock signal has been utilized as an element that provides synchronization on the flow of data. However, an exhaustive timing analysis is needed to determine the maximum clock frequency that can regulate the performance of each logic module in an electronic system. In addition, the clock signal typically represents around 30% of power consumption in synchronous circuits and introduces electromagnetic interference (EMI) due to the rapid fluctuation of electric current flow. For this reason, exclusion of a clock signal allows asynchronous logic to be suitable for low power electronics and circuits that demand noise stability. Moreover, this thesis explores two additional fields that complement asynchronous logic to create a more robust technology that consumes less power — more appropriate for biomedical electronics and space applications. The explored fields grasp fault tolerant schemes that decrease the vulnerability to radiation and strategies to design logic apt to operate in a subthreshold regime (0.3 V). Thus, the main objective of the presented work is to introduce a strategy that combines 1) the benefits of asynchronous circuits, 2) the reduced power consumption achieved at a subthreshold operation, and 3) the radiation hardening that a fault tolerant scheme offers. Specifically, this strategy was implemented on an existing asynchronous system referred to as Null Convention LogicTM ® in order to not only reduce energy, but also to increase the fault tolerance on logic gates that constitute the library of this asynchronous approach.
Received from ProQuest
Santos, Ivan, "Asynchronous Logic Design With Increased Fault Tolerance And Optimized For Subthreshold Operation" (2013). Open Access Theses & Dissertations. 1727.